Field of the Invention
The invention relates to a method for producing sublithographic etching masks for creating structural features or structures in semiconductor products having a large scale of integration.
In semiconductor products having an extremely large scale of integration, such as in integrated semiconductor memories, the structural fineness of the photolithography is often a limiting factor. In the case of a particular photolithography generation having a minimum structural fineness (feature size) F, the size of the smallest elements of a periodic array is expressed by the equation EQU (2.times.F).sup.2 =4F.sup.2.
A point of departure for increasing the packing density of memory cells is the vertical configuration of the memory cells. They are also known as 3-D Sidewall Flash EPROM cells. The active component is constructed as a cylinder, and a first insulating polyspacer (floating gate) is constructed around the cylinder. The floating gate is surrounded by an interpolydielectric and by a further polyring (control gate). Due to the vertical configuration, the lateral insulation oxide is omitted. Through the use of a suitable disposition of the cylinders, a self-adjusted word line is achieved by the growing together of the control gates in one direction, while they are separated orthogonally thereto. However, minimizing the size of the grid period of the cylinders is limited by the feature size of the photolithography technique.